cv

Basics

Name Jonathan Huang
Label Computer Engineer
Github https://jonrhuang.github.io/
Summary Computer Engineering graduate with experience in hardware design, embedded systems, and cloud infrastructure. Skilled in RISC-V architecture, FPGA development, and simulation tools such as Gem5 and Xilinx Vivado. Strong collaborative and leadership background, including mentoring, research, and cross-functional communication.

Work

  • 2024.06 - Present

    Bel Air, Maryland

    Computer Hardware Engineer
    Brown Deer Technology
    • Developing and maintaining four and five-stage 32 RISC-V DSP processors, including comprehensive test packages
    • Leading the design and implementation of 64-bit RISC-V DSP processors
    • Building a custom Theia-based IDE to streamline and automate development workflow and testing
    • Driving development of parameterizable instruction and data caches, compliant with the AXI4 protocol, to reduce cycle counts by up to 20%
    • Synthesizing cores onto FPGAs using Xilinx Vivado
    • Exploring and implementing new potential use cases including CORDIC and MIL-STD-1553
  • 2023.08 - 2024.05

    West Lafayette, Indiana

    Student Researcher
    Purdue University
    • Created a software simulation of the team’s RISC-V core using Gem5
    • Utilized Embench test suites to monitor performance and guide architectural improvements
    • Led architecture development of the cache and ram using Gem5 to enhance memory performance by 15% through configuration optimizations
  • 2023.05 - 2023.08

    Piscataway, New Jersey

    Cloud Engineer
    IEEE
    • Researched methods to increase observability of resource usage on AWS EKS applications
    • Created a comprehensive run book outlining set up instructions for integrating Open Telemetry, Prometheus, and Grafana, ensuring streamlined implementation across current and future applications
    • Developed a lambda function to notify users of real time failures along with essential information within AWS Batch jobs
  • 2022.05 - 2022.08

    Piscataway, New Jersey

    Software Engineer
    IEEE
    • Identified over 15 major and recurring issues with applications or processes by implementing new data science clustering and NLP techniques in Python to process help desk tickets
    • Communicated with the business relations team, database team, and infrastructure team to collect and organize application and licensing data for the migration to a new data storage software

Education

  • 2020.08 - 2024.05

    West Lafayette, Indiana

    Bachelors of Science
    Purdue University
    Computer Engineering

Skills

Languages
System Verilog
Verilog
C
C++
Rust
Bash
Python
Perl
Assembly
TypeScript
ReactJS
Technology/Tools
Linux
Git
Xilinx Vivado
Questasim
FPGA
Jira
AWS
Docker
Gem5
Verilator

Projects

  • Retrieval Augmented Generation (RAG) AI Agent
    • Developed a Retrieval-Augmented Generation (RAG) system using OCI GenAI Agents to enable accurate, document-grounded responses about a clothing brand, ingesting PDFs covering policies such as returns, shipping, and company background
    • Designed and configured a semantic search pipeline by implementing chunking, vector embeddings, and retrieval settings, ensuring high-precision answers sourced directly from the brand’s policy documents
  • 2023.01 - 2023.05
    Multicore Processor
    • Prototyped processor with a five-stage pipeline, two-way set-associative data cache, direct mapped instruction cache, along with MSI cache coherence protocol for dual-multicore.
    • Achieved synchronization support with LL-SC in the data path, along with parallel programs in MIPS assembly
    • Verified components and final integration of design using System Verilog testbenches and the comparison of memory traces with various self-written MIPS test cases